62 lines
3.8 KiB
C
62 lines
3.8 KiB
C
/*
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* Copyright (c) CompanyNameMagicTag 2018-2020. All rights reserved.
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* Project line : Platform And Key Technologies Development
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* Department : CAD Development Department
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* Version : 1.0
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* Date : 2017/10/29
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* Description : The description of xxx project
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* Others : Generated automatically by nManager V4.2
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* History : xxx 2018/05/18 10:43:51 Create file
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*/
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#ifndef __STC_REG_OFFSET_H__
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#define __STC_REG_OFFSET_H__
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/* STC Base address of Module's Register */
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#define dw21v100_STC_BASE (0x40020e00)
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/***************************************************************************** */
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/* dw21v100 STC Registers' Definitions */
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/***************************************************************************** */
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#define dw21v100_STC_STC_CTRL_REG_REG (dw21v100_STC_BASE + 0x80)
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/* STC_CTRL_REG is the data capture control register. */
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#define dw21v100_STC_STC_RX_STATUS_REG_REG (dw21v100_STC_BASE + 0x84)
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/* STC_RX_STATUS_REG is the data capture completion status register for the RX end. */
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#define dw21v100_STC_STC_RX_START_ADDR_REG_REG (dw21v100_STC_BASE + 0x88)
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/* STC_RX_START_ADDR_REG is the SDRAM start address configuration register for the RX end. */
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#define dw21v100_STC_STC_RX_END_ADDR_REG_REG (dw21v100_STC_BASE + 0x8C)
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/* STC_RX_END_ADDR_REG is the SDRAM end address configuration register for the RX end. */
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#define dw21v100_STC_STC_RX_CURR_ADDR_REG_REG (dw21v100_STC_BASE + 0x90)
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/* STC_RX_CURR_ADDR_REG is the SDRAM address writing register for the RX end. */
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#define dw21v100_STC_STC_TX_STATUS_REG_REG (dw21v100_STC_BASE + 0x94)
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/* STC_TX_STATUS_REG is the data capture completion status register for the TX end. */
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#define dw21v100_STC_STC_TX_START_ADDR_REG_REG (dw21v100_STC_BASE + 0x98)
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/* STC_TX_START_ADDR_REG is the SDRAM start address configuration register for the TX end. */
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#define dw21v100_STC_STC_TX_END_ADDR_REG_REG (dw21v100_STC_BASE + 0x9C)
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/* STC_TX_END_ADDR_REG is the SDRAM end address configuration register for the TX end. */
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#define dw21v100_STC_STC_TX_CURR_ADDR_REG_REG (dw21v100_STC_BASE + 0xA0)
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/* STC_TX_CURR_ADDR_REG is the SDRAM address reading register for the TX end. */
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#define dw21v100_STC_STC_DELAY_COUNT_REG_REG (dw21v100_STC_BASE + 0xAC)
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/* STC_DELAY_COUNT_REG is the delay register before data capture stops in collection mode. */
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#define dw21v100_STC_STC_CAP_CTRL_REG_REG (dw21v100_STC_BASE + 0xB0)
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/* STC_CAP_CTRL_REG is the capture mode control register. */
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#define dw21v100_STC_STC_TRIG_MASK_REG_REG (dw21v100_STC_BASE + 0xB4)
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/* STC_TRIG_MASK_REG is the mask data bit register for triggering the data capture mode. */
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#define dw21v100_STC_STC_TRIG_DATA_REG_REG (dw21v100_STC_BASE + 0xB8)
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/* STC_TRIG_MASK_REG is the mask data register for triggering the data capture mode. */
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#define dw21v100_STC_STC_TRIG_ADDR_REG (dw21v100_STC_BASE + 0xBC)
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/* STC_TRIG_ADDR is the SDRAM write address register corresponding to the trigger signal for the RX end. */
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#define dw21v100_STC_PKT_GAP_THRES_REG (dw21v100_STC_BASE + 0xC0)
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/* PKT_GAP_THRES is the packet interval threshold configuration register. */
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#define dw21v100_STC_HADDRM_REG (dw21v100_STC_BASE + 0xC4)
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/* HADDRM is the address register corresponding to the next DDR write. */
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#define dw21v100_STC_DFX_REG_CTRL_REG (dw21v100_STC_BASE + 0xD0)
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/* DFX_REG_CTRL is the DFX data capture control register. */
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#define dw21v100_STC_DFX_REG_CAP_CTRL_REG (dw21v100_STC_BASE + 0xD4)
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/* DFX_REG_CAP_CTRL is the DFX data capture configuration register. */
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#define dw21v100_STC_DFX_REG_DELAY_COUNT_REG (dw21v100_STC_BASE + 0xD8)
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/* DFX_REG_DELAY_COUNT is the delay count configuration register in the DFX trigger mode. */
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#define dw21v100_STC_DFX_REG_PREAM_PAR_REG (dw21v100_STC_BASE + 0xDC)
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/* DFX_REG_PREAM_PAR is the latch peak-to-average ratio register in DFX trigger mode. */
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#endif // __STC_REG_OFFSET_H__
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