679 lines
27 KiB
C
679 lines
27 KiB
C
/*
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* Copyright (c) CompanyNameMagicTag 2018-2019. All rights reserved.
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* File name : crg_reg_reg_offset_field.h
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* Project line : Platform And Key Technologies Development
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* Department : CAD Development Department
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* Version : 1.0
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* Date : 2013/3/10
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* Description : The description of xxx project
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* Others : Generated automatically by nManager V4.2
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* History : xxx 2018/05/19 17:32:50 Create file
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*/
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#ifndef __CRG_REG_OFFSET_FIELD_H__
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#define __CRG_REG_OFFSET_FIELD_H__
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#define CRG_REG_APLL_LOCK_LEN 1
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#define CRG_REG_APLL_LOCK_OFFSET 0
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#define CRG_REG_APLL_DSMPD_LEN 1
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#define CRG_REG_APLL_DSMPD_OFFSET 31
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#define CRG_REG_APLL_BYPASS_LEN 1
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#define CRG_REG_APLL_BYPASS_OFFSET 30
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#define CRG_REG_APLL_POSTDIV2_LEN 3
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#define CRG_REG_APLL_POSTDIV2_OFFSET 27
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#define CRG_REG_APLL_POSTDIV1_LEN 3
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#define CRG_REG_APLL_POSTDIV1_OFFSET 24
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#define CRG_REG_APLL_FRAC_LEN 24
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#define CRG_REG_APLL_FRAC_OFFSET 0
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#define CRG_REG_APLL_DACPD_LEN 1
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#define CRG_REG_APLL_DACPD_OFFSET 29
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#define CRG_REG_APLL_PD_LEN 1
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#define CRG_REG_APLL_PD_OFFSET 21
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#define CRG_REG_APLL_FOUTVCOPD_LEN 1
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#define CRG_REG_APLL_FOUTVCOPD_OFFSET 20
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#define CRG_REG_APLL_FOUTPOSTDIVPD_LEN 1
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#define CRG_REG_APLL_FOUTPOSTDIVPD_OFFSET 19
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#define CRG_REG_APLL_FOUT4PHASEPD_LEN 1
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#define CRG_REG_APLL_FOUT4PHASEPD_OFFSET 18
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#define CRG_REG_APLL_REFDIV_LEN 6
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#define CRG_REG_APLL_REFDIV_OFFSET 12
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#define CRG_REG_APLL_FBDIV_LEN 12
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#define CRG_REG_APLL_FBDIV_OFFSET 0
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#define CRG_REG_NTB_CLK_EN_LEN 1
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#define CRG_REG_NTB_CLK_EN_OFFSET 25
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#define CRG_REG_PWM1_CLK_EN_LEN 1
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#define CRG_REG_PWM1_CLK_EN_OFFSET 24
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#define CRG_REG_MMU_CLK_EN_LEN 1
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#define CRG_REG_MMU_CLK_EN_OFFSET 23
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#define CRG_REG_TSENSOR_CLK_1M_EN_LEN 1
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#define CRG_REG_TSENSOR_CLK_1M_EN_OFFSET 22
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#define CRG_REG_RSA_CLK_EN_LEN 1
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#define CRG_REG_RSA_CLK_EN_OFFSET 21
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#define CRG_REG_OSC_APB_CLK_EN_LEN 1
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#define CRG_REG_OSC_APB_CLK_EN_OFFSET 20
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#define CRG_REG_PWM_APB_CLK_EN_LEN 1
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#define CRG_REG_PWM_APB_CLK_EN_OFFSET 19
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#define CRG_REG_PWM_CLK_EN_LEN 1
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#define CRG_REG_PWM_CLK_EN_OFFSET 18
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#define CRG_REG_SFC_BUS_CLK_EN_LEN 1
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#define CRG_REG_SFC_BUS_CLK_EN_OFFSET 17
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#define CRG_REG_SFC_CLK_EN_LEN 1
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#define CRG_REG_SFC_CLK_EN_OFFSET 16
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#define CRG_REG_STC_BUS_CLK_EN_LEN 1
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#define CRG_REG_STC_BUS_CLK_EN_OFFSET 15
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#define CRG_REG_SPACC_BUS_CLK_EN_LEN 1
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#define CRG_REG_SPACC_BUS_CLK_EN_OFFSET 14
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#define CRG_REG_SPACC_CLK_EN_LEN 1
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#define CRG_REG_SPACC_CLK_EN_OFFSET 13
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#define CRG_REG_BUS_CLK_EN_LEN 1
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#define CRG_REG_BUS_CLK_EN_OFFSET 12
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#define CRG_REG_CM3_FCLK_EN_LEN 1
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#define CRG_REG_CM3_FCLK_EN_OFFSET 11
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#define CRG_REG_CM3_HCLK_EN_LEN 1
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#define CRG_REG_CM3_HCLK_EN_OFFSET 10
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#define CRG_REG_XTAL_AFTER_GATE_CLK_EN_LEN 1
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#define CRG_REG_XTAL_AFTER_GATE_CLK_EN_OFFSET 9
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#define CRG_REG_ADC_IN_CLK_EN_LEN 1
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#define CRG_REG_ADC_IN_CLK_EN_OFFSET 8
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#define CRG_REG_EFUSE_CLK_EN_LEN 1
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#define CRG_REG_EFUSE_CLK_EN_OFFSET 7
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#define CRG_REG_LED_25M_CLK_EN_LEN 1
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#define CRG_REG_LED_25M_CLK_EN_OFFSET 6
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#define CRG_REG_TIMER5_CLK_EN_LEN 1
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#define CRG_REG_TIMER5_CLK_EN_OFFSET 5
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#define CRG_REG_TIMER4_CLK_EN_LEN 1
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#define CRG_REG_TIMER4_CLK_EN_OFFSET 4
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#define CRG_REG_TIMER3_CLK_EN_LEN 1
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#define CRG_REG_TIMER3_CLK_EN_OFFSET 3
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#define CRG_REG_TIMER2_CLK_EN_LEN 1
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#define CRG_REG_TIMER2_CLK_EN_OFFSET 2
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#define CRG_REG_TIMER1_CLK_EN_LEN 1
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#define CRG_REG_TIMER1_CLK_EN_OFFSET 1
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#define CRG_REG_TIMER0_CLK_EN_LEN 1
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#define CRG_REG_TIMER0_CLK_EN_OFFSET 0
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#define CRG_REG_TIME_CNT1_CLK_EN_LEN 1
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#define CRG_REG_TIME_CNT1_CLK_EN_OFFSET 22
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#define CRG_REG_SSP2_CLK_EN_LEN 1
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#define CRG_REG_SSP2_CLK_EN_OFFSET 21
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#define CRG_REG_STC_CLK_EN_LEN 1
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#define CRG_REG_STC_CLK_EN_OFFSET 20
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#define CRG_REG_DA_DATA_CLK_EN_LEN 1
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#define CRG_REG_DA_DATA_CLK_EN_OFFSET 19
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#define CRG_REG_APB_REMAP_AFE_CLK_EN_LEN 1
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#define CRG_REG_APB_REMAP_AFE_CLK_EN_OFFSET 18
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#define CRG_REG_RNG_CLK_EN_LEN 1
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#define CRG_REG_RNG_CLK_EN_OFFSET 17
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#define CRG_REG_TIME_CNT_APB_CLK_EN_LEN 1
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#define CRG_REG_TIME_CNT_APB_CLK_EN_OFFSET 16
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#define CRG_REG_TIME_CNT_CLK_EN_LEN 1
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#define CRG_REG_TIME_CNT_CLK_EN_OFFSET 15
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#define CRG_REG_UART1_CLK_EN_LEN 1
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#define CRG_REG_UART1_CLK_EN_OFFSET 14
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#define CRG_REG_UART0_CLK_EN_LEN 1
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#define CRG_REG_UART0_CLK_EN_OFFSET 13
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#define CRG_REG_UART1_APB_CLK_EN_LEN 1
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#define CRG_REG_UART1_APB_CLK_EN_OFFSET 12
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#define CRG_REG_UART0_APB_CLK_EN_LEN 1
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#define CRG_REG_UART0_APB_CLK_EN_OFFSET 11
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#define CRG_REG_SEC_APB_CLK_EN_LEN 1
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#define CRG_REG_SEC_APB_CLK_EN_OFFSET 10
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#define CRG_REG_BUCK_REG_CLK_EN_LEN 1
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#define CRG_REG_BUCK_REG_CLK_EN_OFFSET 9
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#define CRG_REG_LED_CLK_EN_LEN 1
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#define CRG_REG_LED_CLK_EN_OFFSET 8
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#define CRG_REG_CLK_1M_PMC_EN_LEN 1
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#define CRG_REG_CLK_1M_PMC_EN_OFFSET 7
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#define CRG_REG_PCLK_PMC_EN_LEN 1
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#define CRG_REG_PCLK_PMC_EN_OFFSET 6
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#define CRG_REG_GPIO_CLK_EN_LEN 1
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#define CRG_REG_GPIO_CLK_EN_OFFSET 5
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#define CRG_REG_I2C_CLK_EN_LEN 1
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#define CRG_REG_I2C_CLK_EN_OFFSET 4
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#define CRG_REG_SSP_CLK_EN_LEN 1
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#define CRG_REG_SSP_CLK_EN_OFFSET 3
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#define CRG_REG_SYS_CTRL_CLK_EN_LEN 1
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#define CRG_REG_SYS_CTRL_CLK_EN_OFFSET 2
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#define CRG_REG_TIMER_APB_CLK_EN_LEN 1
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#define CRG_REG_TIMER_APB_CLK_EN_OFFSET 1
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#define CRG_REG_APB_CLK_EN_LEN 1
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#define CRG_REG_APB_CLK_EN_OFFSET 0
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#define CRG_REG_NTB_CLK_STAT_LEN 1
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#define CRG_REG_NTB_CLK_STAT_OFFSET 25
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#define CRG_REG_PWM1_CLK_STAT_LEN 1
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#define CRG_REG_PWM1_CLK_STAT_OFFSET 24
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#define CRG_REG_MMU_CLK_STAT_LEN 1
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#define CRG_REG_MMU_CLK_STAT_OFFSET 23
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#define CRG_REG_TSENSOR_CLK_1M_STAT_LEN 1
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#define CRG_REG_TSENSOR_CLK_1M_STAT_OFFSET 22
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#define CRG_REG_RSA_CLK_STAT_LEN 1
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#define CRG_REG_RSA_CLK_STAT_OFFSET 21
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#define CRG_REG_OSC_APB_CLK_STAT_LEN 1
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#define CRG_REG_OSC_APB_CLK_STAT_OFFSET 20
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#define CRG_REG_PWM_APB_CLK_STAT_LEN 1
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#define CRG_REG_PWM_APB_CLK_STAT_OFFSET 19
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#define CRG_REG_PWM_CLK_STAT_LEN 1
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#define CRG_REG_PWM_CLK_STAT_OFFSET 18
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#define CRG_REG_SFC_BUS_CLK_STAT_LEN 1
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#define CRG_REG_SFC_BUS_CLK_STAT_OFFSET 17
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#define CRG_REG_SFC_CLK_STAT_LEN 1
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#define CRG_REG_SFC_CLK_STAT_OFFSET 16
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#define CRG_REG_STC_BUS_CLK_STAT_LEN 1
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#define CRG_REG_STC_BUS_CLK_STAT_OFFSET 15
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#define CRG_REG_SPACC_BUS_CLK_STAT_LEN 1
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#define CRG_REG_SPACC_BUS_CLK_STAT_OFFSET 14
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#define CRG_REG_SPACC_CLK_STAT_LEN 1
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#define CRG_REG_SPACC_CLK_STAT_OFFSET 13
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#define CRG_REG_BUS_CLK_STAT_LEN 1
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#define CRG_REG_BUS_CLK_STAT_OFFSET 12
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#define CRG_REG_CM3_FCLK_STAT_LEN 1
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#define CRG_REG_CM3_FCLK_STAT_OFFSET 10
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#define CRG_REG_XTAL_AFTER_GATE_CLK_STAT_LEN 1
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#define CRG_REG_XTAL_AFTER_GATE_CLK_STAT_OFFSET 9
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#define CRG_REG_ADC_IN_CLK_STAT_LEN 1
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#define CRG_REG_ADC_IN_CLK_STAT_OFFSET 8
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#define CRG_REG_EFUSE_CLK_STAT_LEN 1
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#define CRG_REG_EFUSE_CLK_STAT_OFFSET 7
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#define CRG_REG_LED_25M_CLK_STAT_LEN 1
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#define CRG_REG_LED_25M_CLK_STAT_OFFSET 6
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#define CRG_REG_TIMER5_CLK_STAT_LEN 1
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#define CRG_REG_TIMER5_CLK_STAT_OFFSET 5
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#define CRG_REG_TIMER4_CLK_STAT_LEN 1
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#define CRG_REG_TIMER4_CLK_STAT_OFFSET 4
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#define CRG_REG_TIMER3_CLK_STAT_LEN 1
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#define CRG_REG_TIMER3_CLK_STAT_OFFSET 3
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#define CRG_REG_TIMER2_CLK_STAT_LEN 1
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#define CRG_REG_TIMER2_CLK_STAT_OFFSET 2
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#define CRG_REG_TIMER1_CLK_STAT_LEN 1
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#define CRG_REG_TIMER1_CLK_STAT_OFFSET 1
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#define CRG_REG_TIMER0_CLK_STAT_LEN 1
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#define CRG_REG_TIMER0_CLK_STAT_OFFSET 0
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#define CRG_REG_TIME_CNT1_CLK_STAT_LEN 1
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#define CRG_REG_TIME_CNT1_CLK_STAT_OFFSET 25
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#define CRG_REG_PHY_AP_CLK_STAT_LEN 1
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#define CRG_REG_PHY_AP_CLK_STAT_OFFSET 24
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#define CRG_REG_SPC_CLK_STAT_LEN 1
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#define CRG_REG_SPC_CLK_STAT_OFFSET 23
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#define CRG_REG_PHY_CLK_STAT_LEN 1
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#define CRG_REG_PHY_CLK_STAT_OFFSET 22
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#define CRG_REG_SSP2_CLK_STAT_LEN 1
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#define CRG_REG_SSP2_CLK_STAT_OFFSET 21
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#define CRG_REG_STC_CLK_STAT_LEN 1
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#define CRG_REG_STC_CLK_STAT_OFFSET 20
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#define CRG_REG_DA_DATA_CLK_STAT_LEN 1
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#define CRG_REG_DA_DATA_CLK_STAT_OFFSET 19
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#define CRG_REG_APB_REMAP_AFE_CLK_STAT_LEN 1
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#define CRG_REG_APB_REMAP_AFE_CLK_STAT_OFFSET 18
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#define CRG_REG_RNG_CLK_STAT_LEN 1
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#define CRG_REG_RNG_CLK_STAT_OFFSET 17
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#define CRG_REG_TIME_CNT_APB_CLK_STAT_LEN 1
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#define CRG_REG_TIME_CNT_APB_CLK_STAT_OFFSET 16
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#define CRG_REG_TIME_CNT_CLK_STAT_LEN 1
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#define CRG_REG_TIME_CNT_CLK_STAT_OFFSET 15
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#define CRG_REG_UART1_CLK_STAT_LEN 1
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#define CRG_REG_UART1_CLK_STAT_OFFSET 14
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#define CRG_REG_UART0_CLK_STAT_LEN 1
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#define CRG_REG_UART0_CLK_STAT_OFFSET 13
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#define CRG_REG_UART1_APB_CLK_STAT_LEN 1
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#define CRG_REG_UART1_APB_CLK_STAT_OFFSET 12
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#define CRG_REG_UART0_APB_CLK_STAT_LEN 1
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#define CRG_REG_UART0_APB_CLK_STAT_OFFSET 11
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#define CRG_REG_SEC_APB_CLK_STAT_LEN 1
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#define CRG_REG_SEC_APB_CLK_STAT_OFFSET 10
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#define CRG_REG_BUCK_REG_CLK_STAT_LEN 1
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#define CRG_REG_BUCK_REG_CLK_STAT_OFFSET 9
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#define CRG_REG_LED_CLK_STAT_LEN 1
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#define CRG_REG_LED_CLK_STAT_OFFSET 8
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#define CRG_REG_CLK_1M_PMC_STAT_LEN 1
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#define CRG_REG_CLK_1M_PMC_STAT_OFFSET 7
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#define CRG_REG_PCLK_PMC_STAT_LEN 1
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#define CRG_REG_PCLK_PMC_STAT_OFFSET 6
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#define CRG_REG_GPIO_CLK_STAT_LEN 1
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#define CRG_REG_GPIO_CLK_STAT_OFFSET 5
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#define CRG_REG_I2C_CLK_STAT_LEN 1
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#define CRG_REG_I2C_CLK_STAT_OFFSET 4
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#define CRG_REG_SSP_CLK_STAT_LEN 1
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#define CRG_REG_SSP_CLK_STAT_OFFSET 3
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#define CRG_REG_SYS_CTRL_CLK_STAT_LEN 1
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#define CRG_REG_SYS_CTRL_CLK_STAT_OFFSET 2
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#define CRG_REG_TIMER_APB_CLK_STAT_LEN 1
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#define CRG_REG_TIMER_APB_CLK_STAT_OFFSET 1
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#define CRG_REG_APB_CLK_STAT_LEN 1
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#define CRG_REG_APB_CLK_STAT_OFFSET 0
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#define CRG_REG_NTB_CLK_SEL_LEN 1
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#define CRG_REG_NTB_CLK_SEL_OFFSET 14
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#define CRG_REG_PWM_CLK_SEL_LEN 1
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#define CRG_REG_PWM_CLK_SEL_OFFSET 13
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#define CRG_REG_TIMER5_CLK_SEL_LEN 1
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#define CRG_REG_TIMER5_CLK_SEL_OFFSET 12
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#define CRG_REG_TIMER4_CLK_SEL_LEN 1
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#define CRG_REG_TIMER4_CLK_SEL_OFFSET 11
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#define CRG_REG_SFC_CLK_DIV_LEN 4
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#define CRG_REG_SFC_CLK_DIV_OFFSET 5
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#define CRG_REG_SFC_CLK_SEL_LEN 1
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#define CRG_REG_SFC_CLK_SEL_OFFSET 4
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#define CRG_REG_UART_CLK_SEL_LEN 1
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#define CRG_REG_UART_CLK_SEL_OFFSET 3
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#define CRG_REG_ARM_CLK_SEL_LEN 2
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#define CRG_REG_ARM_CLK_SEL_OFFSET 0
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#define CRG_REG_PWM1_SRST_REQ_LEN 1
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#define CRG_REG_PWM1_SRST_REQ_OFFSET 31
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#define CRG_REG_MMU_SRST_REQ_LEN 1
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#define CRG_REG_MMU_SRST_REQ_OFFSET 30
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#define CRG_REG_RSA_SRST_REQ_LEN 1
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#define CRG_REG_RSA_SRST_REQ_OFFSET 29
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#define CRG_REG_TSENSOR_SRST_REQ_LEN 1
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#define CRG_REG_TSENSOR_SRST_REQ_OFFSET 28
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#define CRG_REG_SPACC_SRST_REQ_LEN 1
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#define CRG_REG_SPACC_SRST_REQ_OFFSET 27
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#define CRG_REG_PWM_SRST_REQ_LEN 1
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#define CRG_REG_PWM_SRST_REQ_OFFSET 26
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#define CRG_REG_SSP2_SRST_REQ_LEN 1
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#define CRG_REG_SSP2_SRST_REQ_OFFSET 25
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#define CRG_REG_SARADC_CIC_SRST_REQ_LEN 1
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#define CRG_REG_SARADC_CIC_SRST_REQ_OFFSET 24
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#define CRG_REG_BUCK_REG_SRST_REQ_LEN 1
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#define CRG_REG_BUCK_REG_SRST_REQ_OFFSET 23
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#define CRG_REG_LED_25M_SRST_REQ_LEN 1
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#define CRG_REG_LED_25M_SRST_REQ_OFFSET 22
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#define CRG_REG_TIME_CNT_SRST_REQ_LEN 1
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#define CRG_REG_TIME_CNT_SRST_REQ_OFFSET 21
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#define CRG_REG_ADC_IN_SRST_REQ_LEN 1
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#define CRG_REG_ADC_IN_SRST_REQ_OFFSET 20
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#define CRG_REG_EFUSE_SRST_REQ_LEN 1
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#define CRG_REG_EFUSE_SRST_REQ_OFFSET 19
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#define CRG_REG_LED_SRST_REQ_LEN 1
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#define CRG_REG_LED_SRST_REQ_OFFSET 18
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#define CRG_REG_SSP_SRST_REQ_LEN 1
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#define CRG_REG_SSP_SRST_REQ_OFFSET 17
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#define CRG_REG_STC_SRST_REQ_LEN 1
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#define CRG_REG_STC_SRST_REQ_OFFSET 16
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#define CRG_REG_BUS_SRST_REQ_LEN 1
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#define CRG_REG_BUS_SRST_REQ_OFFSET 15
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#define CRG_REG_ARM_SRST_REQ_LEN 1
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#define CRG_REG_ARM_SRST_REQ_OFFSET 14
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#define CRG_REG_GPIO_SRST_REQ_LEN 1
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#define CRG_REG_GPIO_SRST_REQ_OFFSET 13
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#define CRG_REG_I2C_SRST_REQ_LEN 1
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#define CRG_REG_I2C_SRST_REQ_OFFSET 12
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#define CRG_REG_UART1_SRST_REQ_LEN 1
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#define CRG_REG_UART1_SRST_REQ_OFFSET 11
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#define CRG_REG_UART0_SRST_REQ_LEN 1
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#define CRG_REG_UART0_SRST_REQ_OFFSET 10
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#define CRG_REG_TIMER5_SRST_REQ_LEN 1
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#define CRG_REG_TIMER5_SRST_REQ_OFFSET 9
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#define CRG_REG_TIMER4_SRST_REQ_LEN 1
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#define CRG_REG_TIMER4_SRST_REQ_OFFSET 8
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#define CRG_REG_TIMER3_SRST_REQ_LEN 1
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#define CRG_REG_TIMER3_SRST_REQ_OFFSET 7
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#define CRG_REG_TIMER2_SRST_REQ_LEN 1
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#define CRG_REG_TIMER2_SRST_REQ_OFFSET 6
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#define CRG_REG_TIMER1_SRST_REQ_LEN 1
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#define CRG_REG_TIMER1_SRST_REQ_OFFSET 5
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#define CRG_REG_TIMER0_SRST_REQ_LEN 1
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#define CRG_REG_TIMER0_SRST_REQ_OFFSET 4
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#define CRG_REG_RNG_SRST_REQ_LEN 1
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#define CRG_REG_RNG_SRST_REQ_OFFSET 3
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#define CRG_REG_SFC_SRST_REQ_LEN 1
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#define CRG_REG_SFC_SRST_REQ_OFFSET 2
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#define CRG_REG_PMC_SRST_REQ_LEN 1
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#define CRG_REG_PMC_SRST_REQ_OFFSET 1
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#define CRG_REG_WDT_RST_EN_LEN 1
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#define CRG_REG_WDT_RST_EN_OFFSET 0
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#define CRG_REG_PWM_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_PWM_CLK_SLEEP_EN_OFFSET 31
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#define CRG_REG_PWM_APB_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_PWM_APB_CLK_SLEEP_EN_OFFSET 30
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#define CRG_REG_TIME_CNT_APB_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_TIME_CNT_APB_CLK_SLEEP_EN_OFFSET 29
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#define CRG_REG_CRG_REG_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_CRG_REG_CLK_SLEEP_EN_OFFSET 28
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#define CRG_REG_BUCK_REG_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_BUCK_REG_CLK_SLEEP_EN_OFFSET 27
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#define CRG_REG_SFC_BUS_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_SFC_BUS_CLK_SLEEP_EN_OFFSET 26
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#define CRG_REG_CM3_HCLK_SLEEP_EN_LEN 1
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#define CRG_REG_CM3_HCLK_SLEEP_EN_OFFSET 25
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#define CRG_REG_PCLK_PMC_SLEEP_EN_LEN 1
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#define CRG_REG_PCLK_PMC_SLEEP_EN_OFFSET 24
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#define CRG_REG_CLK_1M_PMC_SLEEP_EN_LEN 1
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#define CRG_REG_CLK_1M_PMC_SLEEP_EN_OFFSET 23
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#define CRG_REG_XTAL_AFTER_GATE_SLEEP_EN_LEN 1
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#define CRG_REG_XTAL_AFTER_GATE_SLEEP_EN_OFFSET 22
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#define CRG_REG_LED_25M_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_LED_25M_CLK_SLEEP_EN_OFFSET 21
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#define CRG_REG_TIMER0_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_TIMER0_CLK_SLEEP_EN_OFFSET 20
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#define CRG_REG_TIMER1_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_TIMER1_CLK_SLEEP_EN_OFFSET 19
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#define CRG_REG_TIMER2_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_TIMER2_CLK_SLEEP_EN_OFFSET 18
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#define CRG_REG_TIMER3_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_TIMER3_CLK_SLEEP_EN_OFFSET 17
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#define CRG_REG_TIMER4_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_TIMER4_CLK_SLEEP_EN_OFFSET 16
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#define CRG_REG_TIMER5_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_TIMER5_CLK_SLEEP_EN_OFFSET 15
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#define CRG_REG_BUS_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_BUS_CLK_SLEEP_EN_OFFSET 14
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#define CRG_REG_APB_REMAP_AFE_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_APB_REMAP_AFE_CLK_SLEEP_EN_OFFSET 13
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#define CRG_REG_APB_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_APB_CLK_SLEEP_EN_OFFSET 12
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#define CRG_REG_SSP_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_SSP_CLK_SLEEP_EN_OFFSET 11
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#define CRG_REG_UART0_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_UART0_CLK_SLEEP_EN_OFFSET 10
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#define CRG_REG_UART1_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_UART1_CLK_SLEEP_EN_OFFSET 9
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#define CRG_REG_I2C_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_I2C_CLK_SLEEP_EN_OFFSET 8
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#define CRG_REG_GPIO_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_GPIO_CLK_SLEEP_EN_OFFSET 7
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#define CRG_REG_LED_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_LED_CLK_SLEEP_EN_OFFSET 6
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#define CRG_REG_SFCX2_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_SFCX2_CLK_SLEEP_EN_OFFSET 5
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#define CRG_REG_SFC_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_SFC_CLK_SLEEP_EN_OFFSET 4
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#define CRG_REG_PHY_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_PHY_CLK_SLEEP_EN_OFFSET 3
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#define CRG_REG_ADC_IN_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_ADC_IN_CLK_SLEEP_EN_OFFSET 2
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#define CRG_REG_DA_DATA_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_DA_DATA_CLK_SLEEP_EN_OFFSET 1
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#define CRG_REG_TIME_CNT_CLK_SLEEP_EN_LEN 1
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#define CRG_REG_TIME_CNT_CLK_SLEEP_EN_OFFSET 0
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#define CRG_REG_PHY_CLK_EN_LEN 1
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#define CRG_REG_PHY_CLK_EN_OFFSET 30
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#define CRG_REG_SPC_CLK_EN_LEN 1
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#define CRG_REG_SPC_CLK_EN_OFFSET 29
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#define CRG_REG_PHY_AP_CLK_EN_LEN 1
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#define CRG_REG_PHY_AP_CLK_EN_OFFSET 28
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#define CRG_REG_PHY_TXPA_CLK_SW_EN_LEN 2
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#define CRG_REG_PHY_TXPA_CLK_SW_EN_OFFSET 26
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#define CRG_REG_PHY_ISP_CLK_SW_EN_LEN 2
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#define CRG_REG_PHY_ISP_CLK_SW_EN_OFFSET 24
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#define CRG_REG_D8LPF_CLK_SW_EN_LEN 2
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#define CRG_REG_D8LPF_CLK_SW_EN_OFFSET 22
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#define CRG_REG_D4LPF_CLK_SW_EN_LEN 2
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#define CRG_REG_D4LPF_CLK_SW_EN_OFFSET 20
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#define CRG_REG_PHY_SYNC_CLK_SW_EN_LEN 2
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#define CRG_REG_PHY_SYNC_CLK_SW_EN_OFFSET 16
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#define CRG_REG_PHY_FEC_TURBO_CLK_SW_EN_LEN 2
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#define CRG_REG_PHY_FEC_TURBO_CLK_SW_EN_OFFSET 14
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#define CRG_REG_PHY_FEC_CLK_SW_EN_LEN 2
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#define CRG_REG_PHY_FEC_CLK_SW_EN_OFFSET 12
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#define CRG_REG_PHY_FREQ_ROTATE_CLK_SW_EN_LEN 2
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#define CRG_REG_PHY_FREQ_ROTATE_CLK_SW_EN_OFFSET 10
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#define CRG_REG_PHY_FFT_CLK_SW_EN_LEN 2
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#define CRG_REG_PHY_FFT_CLK_SW_EN_OFFSET 8
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#define CRG_REG_PHY_CS_CLK_SW_EN_LEN 2
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#define CRG_REG_PHY_CS_CLK_SW_EN_OFFSET 6
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#define CRG_REG_PHY_RX_CLK_SW_EN_LEN 2
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#define CRG_REG_PHY_RX_CLK_SW_EN_OFFSET 4
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#define CRG_REG_PHY_TX_CLK_SW_EN_LEN 2
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#define CRG_REG_PHY_TX_CLK_SW_EN_OFFSET 2
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#define CRG_REG_PHY_NBI_CLK_SW_EN_LEN 2
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#define CRG_REG_PHY_NBI_CLK_SW_EN_OFFSET 0
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#define CRG_REG_MAC2PHY_RX_SRST_REQ_LEN 1
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#define CRG_REG_MAC2PHY_RX_SRST_REQ_OFFSET 31
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#define CRG_REG_MAC2PHY_TX_SRST_REQ_LEN 1
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#define CRG_REG_MAC2PHY_TX_SRST_REQ_OFFSET 30
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#define CRG_REG_PHY_CTRL_SRST_REQ_LEN 1
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#define CRG_REG_PHY_CTRL_SRST_REQ_OFFSET 29
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#define CRG_REG_PHY_D8LPF_SRST_REQ_LEN 1
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#define CRG_REG_PHY_D8LPF_SRST_REQ_OFFSET 28
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#define CRG_REG_PHY_D4LPF_SRST_REQ_LEN 1
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#define CRG_REG_PHY_D4LPF_SRST_REQ_OFFSET 27
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#define CRG_REG_PHY_ASYNC_PROC_SRST_REQ_LEN 1
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#define CRG_REG_PHY_ASYNC_PROC_SRST_REQ_OFFSET 26
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#define CRG_REG_PHY_LPF_SRST_REQ_LEN 1
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#define CRG_REG_PHY_LPF_SRST_REQ_OFFSET 25
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#define CRG_REG_PHY_RX_CUBIC_SRST_REQ_LEN 1
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#define CRG_REG_PHY_RX_CUBIC_SRST_REQ_OFFSET 24
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#define CRG_REG_PHY_HPF_SRST_REQ_LEN 1
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#define CRG_REG_PHY_HPF_SRST_REQ_OFFSET 23
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#define CRG_REG_PHY_NTB_SRST_REQ_LEN 1
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#define CRG_REG_PHY_NTB_SRST_REQ_OFFSET 22
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#define CRG_REG_PHY_TD_NBI_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_TD_NBI_SRST_REQ_OFFSET 21
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|
#define CRG_REG_PHY_IMP_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_IMP_SRST_REQ_OFFSET 20
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|
#define CRG_REG_PHY_ISP_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_ISP_SRST_REQ_OFFSET 19
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|
#define CRG_REG_PHY_SYNC_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_SYNC_SRST_REQ_OFFSET 18
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|
#define CRG_REG_PHY_SNR_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_SNR_SRST_REQ_OFFSET 17
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|
#define CRG_REG_PHY_DEMAP_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_DEMAP_SRST_REQ_OFFSET 16
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#define CRG_REG_PHY_TXPA_SRST_REQ_LEN 1
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#define CRG_REG_PHY_TXPA_SRST_REQ_OFFSET 15
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#define CRG_REG_SPC_XTAL_SRST_REQ_LEN 1
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|
#define CRG_REG_SPC_XTAL_SRST_REQ_OFFSET 14
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|
#define CRG_REG_SPC_SRST_REQ_LEN 1
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#define CRG_REG_SPC_SRST_REQ_OFFSET 13
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|
#define CRG_REG_PHY_NBI_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_NBI_SRST_REQ_OFFSET 12
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|
#define CRG_REG_PHY_FFT_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_FFT_SRST_REQ_OFFSET 11
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|
#define CRG_REG_PHY_FD_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_FD_SRST_REQ_OFFSET 10
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|
#define CRG_REG_PHY_CS_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_CS_SRST_REQ_OFFSET 9
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|
#define CRG_REG_PHY_AGC_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_AGC_SRST_REQ_OFFSET 8
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#define CRG_REG_PHY_RX_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_RX_SRST_REQ_OFFSET 7
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|
#define CRG_REG_DA_DATA_SRST_REQ_LEN 1
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|
#define CRG_REG_DA_DATA_SRST_REQ_OFFSET 6
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#define CRG_REG_AD_DATA_SRST_REQ_LEN 1
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#define CRG_REG_AD_DATA_SRST_REQ_OFFSET 5
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#define CRG_REG_PHY_TX_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_TX_SRST_REQ_OFFSET 4
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|
#define CRG_REG_PHY_DEFC_SRST_REQ_LEN 1
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#define CRG_REG_PHY_DEFC_SRST_REQ_OFFSET 3
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|
#define CRG_REG_PHY_FEC_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_FEC_SRST_REQ_OFFSET 2
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|
#define CRG_REG_PHY_REG_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_REG_SRST_REQ_OFFSET 1
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|
#define CRG_REG_PHY_SRST_REQ_LEN 1
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|
#define CRG_REG_PHY_SRST_REQ_OFFSET 0
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|
|
#define CRG_REG_PHY_HW_NTB_MASK_LEN 1
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|
#define CRG_REG_PHY_HW_NTB_MASK_OFFSET 31
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#define CRG_REG_PHY_SW_NTB_MASK_LEN 1
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|
#define CRG_REG_PHY_SW_NTB_MASK_OFFSET 30
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|
#define CRG_REG_PHY_DEFC_HW_SRST_REQ_MASK_LEN 1
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|
#define CRG_REG_PHY_DEFC_HW_SRST_REQ_MASK_OFFSET 29
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|
#define CRG_REG_PHY_HW_DEFC_MASK_LEN 1
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|
#define CRG_REG_PHY_HW_DEFC_MASK_OFFSET 28
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|
#define CRG_REG_PHY_SW_DEFC_MASK_LEN 1
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|
#define CRG_REG_PHY_SW_DEFC_MASK_OFFSET 27
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|
#define CRG_REG_PHY_HW_MAC2PHY_RX_MASK_LEN 1
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|
#define CRG_REG_PHY_HW_MAC2PHY_RX_MASK_OFFSET 26
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|
#define CRG_REG_PHY_SW_MAC2PHY_RX_MASK_LEN 1
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|
#define CRG_REG_PHY_SW_MAC2PHY_RX_MASK_OFFSET 25
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|
#define CRG_REG_PHY_HW_MAC2PHY_TX_MASK_LEN 1
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|
#define CRG_REG_PHY_HW_MAC2PHY_TX_MASK_OFFSET 24
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|
#define CRG_REG_PHY_SW_MAC2PHY_TX_MASK_LEN 1
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|
#define CRG_REG_PHY_SW_MAC2PHY_TX_MASK_OFFSET 23
|
|
#define CRG_REG_PHY_HW_CTRL_MASK_LEN 1
|
|
#define CRG_REG_PHY_HW_CTRL_MASK_OFFSET 22
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|
#define CRG_REG_PHY_SW_CTRL_MASK_LEN 1
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|
#define CRG_REG_PHY_SW_CTRL_MASK_OFFSET 21
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|
#define CRG_REG_RX_HW_AD_DATA_MASK_LEN 1
|
|
#define CRG_REG_RX_HW_AD_DATA_MASK_OFFSET 20
|
|
#define CRG_REG_TX_HW_DA_DATA_MASK_LEN 1
|
|
#define CRG_REG_TX_HW_DA_DATA_MASK_OFFSET 19
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|
#define CRG_REG_PHY_HW_DA_DATA_MASK_LEN 1
|
|
#define CRG_REG_PHY_HW_DA_DATA_MASK_OFFSET 18
|
|
#define CRG_REG_PHY_SW_DA_DATA_MASK_LEN 1
|
|
#define CRG_REG_PHY_SW_DA_DATA_MASK_OFFSET 17
|
|
#define CRG_REG_PHY_HW_AD_DATA_MASK_LEN 1
|
|
#define CRG_REG_PHY_HW_AD_DATA_MASK_OFFSET 16
|
|
#define CRG_REG_PHY_SW_AD_DATA_MASK_LEN 1
|
|
#define CRG_REG_PHY_SW_AD_DATA_MASK_OFFSET 15
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|
#define CRG_REG_PHY_D8LPF_HW_SRST_REQ_MASK_LEN 1
|
|
#define CRG_REG_PHY_D8LPF_HW_SRST_REQ_MASK_OFFSET 14
|
|
#define CRG_REG_PHY_D4LPF_HW_SRST_REQ_MASK_LEN 1
|
|
#define CRG_REG_PHY_D4LPF_HW_SRST_REQ_MASK_OFFSET 13
|
|
#define CRG_REG_PHY_SW_NBI_MASK_LEN 1
|
|
#define CRG_REG_PHY_SW_NBI_MASK_OFFSET 12
|
|
#define CRG_REG_PHY_FFT_HW_SRST_REQ_MASK_LEN 1
|
|
#define CRG_REG_PHY_FFT_HW_SRST_REQ_MASK_OFFSET 11
|
|
#define CRG_REG_PHY_FD_HW_SRST_REQ_MASK_LEN 1
|
|
#define CRG_REG_PHY_FD_HW_SRST_REQ_MASK_OFFSET 10
|
|
#define CRG_REG_PHY_CS_HW_SRST_REQ_MASK_LEN 1
|
|
#define CRG_REG_PHY_CS_HW_SRST_REQ_MASK_OFFSET 9
|
|
#define CRG_REG_PHY_AGC_HW_SRST_REQ_MASK_LEN 1
|
|
#define CRG_REG_PHY_AGC_HW_SRST_REQ_MASK_OFFSET 8
|
|
#define CRG_REG_PHY_RX_HW_SRST_REQ_MASK_LEN 1
|
|
#define CRG_REG_PHY_RX_HW_SRST_REQ_MASK_OFFSET 7
|
|
#define CRG_REG_PHY_SW_TX_MASK_LEN 1
|
|
#define CRG_REG_PHY_SW_TX_MASK_OFFSET 6
|
|
#define CRG_REG_PHY_HW_TX_MASK_LEN 1
|
|
#define CRG_REG_PHY_HW_TX_MASK_OFFSET 5
|
|
#define CRG_REG_PHY_TX_HW_SRST_REQ_MASK_LEN 1
|
|
#define CRG_REG_PHY_TX_HW_SRST_REQ_MASK_OFFSET 4
|
|
#define CRG_REG_PHY_SW_FEC_MASK_LEN 1
|
|
#define CRG_REG_PHY_SW_FEC_MASK_OFFSET 3
|
|
#define CRG_REG_PHY_FEC_HW_SRST_REQ_MASK_LEN 1
|
|
#define CRG_REG_PHY_FEC_HW_SRST_REQ_MASK_OFFSET 2
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|
#define CRG_REG_PHY_HW_FEC_MASK_LEN 1
|
|
#define CRG_REG_PHY_HW_FEC_MASK_OFFSET 1
|
|
#define CRG_REG_PHY_HW_SRST_REQ_MASK_LEN 1
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|
#define CRG_REG_PHY_HW_SRST_REQ_MASK_OFFSET 0
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|
|
|
#define CRG_REG_RAM_CLK_GT_EN_LEN 32
|
|
#define CRG_REG_RAM_CLK_GT_EN_OFFSET 0
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|
|
|
#define CRG_REG_CODEROM_CLK_GT_EN_LEN 1
|
|
#define CRG_REG_CODEROM_CLK_GT_EN_OFFSET 1
|
|
#define CRG_REG_ROM_CLK_GT_EN_LEN 1
|
|
#define CRG_REG_ROM_CLK_GT_EN_OFFSET 0
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|
|
|
#define CRG_REG_SPC_RST_MASK_LEN 1
|
|
#define CRG_REG_SPC_RST_MASK_OFFSET 0
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|
|
|
#define CRG_REG_TIME_CNT1_CLK_SLEEP_EN_LEN 1
|
|
#define CRG_REG_TIME_CNT1_CLK_SLEEP_EN_OFFSET 6
|
|
#define CRG_REG_NTB_CLK_SLEEP_EN_LEN 1
|
|
#define CRG_REG_NTB_CLK_SLEEP_EN_OFFSET 5
|
|
#define CRG_REG_PWM1_CLK_SLEEP_EN_LEN 1
|
|
#define CRG_REG_PWM1_CLK_SLEEP_EN_OFFSET 4
|
|
#define CRG_REG_MMU_CLK_SLEEP_EN_LEN 1
|
|
#define CRG_REG_MMU_CLK_SLEEP_EN_OFFSET 3
|
|
#define CRG_REG_TSENSOR_CLK_1M_SLEEP_EN_LEN 1
|
|
#define CRG_REG_TSENSOR_CLK_1M_SLEEP_EN_OFFSET 2
|
|
#define CRG_REG_SSP2_CLK_SLEEP_EN_LEN 1
|
|
#define CRG_REG_SSP2_CLK_SLEEP_EN_OFFSET 1
|
|
#define CRG_REG_OSC_APB_CLK_SLEEP_EN_LEN 1
|
|
#define CRG_REG_OSC_APB_CLK_SLEEP_EN_OFFSET 0
|
|
|
|
#define CRG_REG_PWM_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_PWM_CLK_DSLEEP_EN_OFFSET 31
|
|
#define CRG_REG_PWM_APB_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_PWM_APB_CLK_DSLEEP_EN_OFFSET 30
|
|
#define CRG_REG_TIME_CNT_APB_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_TIME_CNT_APB_CLK_DSLEEP_EN_OFFSET 29
|
|
#define CRG_REG_CRG_REG_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_CRG_REG_CLK_DSLEEP_EN_OFFSET 28
|
|
#define CRG_REG_BUCK_REG_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_BUCK_REG_CLK_DSLEEP_EN_OFFSET 27
|
|
#define CRG_REG_SFC_BUS_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_SFC_BUS_CLK_DSLEEP_EN_OFFSET 26
|
|
#define CRG_REG_CM3_HCLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_CM3_HCLK_DSLEEP_EN_OFFSET 25
|
|
#define CRG_REG_PCLK_PMC_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_PCLK_PMC_DSLEEP_EN_OFFSET 24
|
|
#define CRG_REG_CLK_1M_PMC_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_CLK_1M_PMC_DSLEEP_EN_OFFSET 23
|
|
#define CRG_REG_XTAL_AFTER_GATE_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_XTAL_AFTER_GATE_DSLEEP_EN_OFFSET 22
|
|
#define CRG_REG_LED_25M_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_LED_25M_CLK_DSLEEP_EN_OFFSET 21
|
|
#define CRG_REG_TIMER0_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_TIMER0_CLK_DSLEEP_EN_OFFSET 20
|
|
#define CRG_REG_TIMER1_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_TIMER1_CLK_DSLEEP_EN_OFFSET 19
|
|
#define CRG_REG_TIMER2_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_TIMER2_CLK_DSLEEP_EN_OFFSET 18
|
|
#define CRG_REG_TIMER3_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_TIMER3_CLK_DSLEEP_EN_OFFSET 17
|
|
#define CRG_REG_TIMER4_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_TIMER4_CLK_DSLEEP_EN_OFFSET 16
|
|
#define CRG_REG_TIMER5_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_TIMER5_CLK_DSLEEP_EN_OFFSET 15
|
|
#define CRG_REG_BUS_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_BUS_CLK_DSLEEP_EN_OFFSET 14
|
|
#define CRG_REG_APB_REMAP_AFE_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_APB_REMAP_AFE_CLK_DSLEEP_EN_OFFSET 13
|
|
#define CRG_REG_APB_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_APB_CLK_DSLEEP_EN_OFFSET 12
|
|
#define CRG_REG_SSP_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_SSP_CLK_DSLEEP_EN_OFFSET 11
|
|
#define CRG_REG_UART0_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_UART0_CLK_DSLEEP_EN_OFFSET 10
|
|
#define CRG_REG_UART1_CLK_DSLEEP_EN_LEN 1
|
|
#define CRG_REG_UART1_CLK_DSLEEP_EN_OFFSET 9
|
|
#define CRG_REG_I2C_CLK_DSLEEP_EN_LEN 1
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#define CRG_REG_I2C_CLK_DSLEEP_EN_OFFSET 8
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#define CRG_REG_GPIO_CLK_DSLEEP_EN_LEN 1
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#define CRG_REG_GPIO_CLK_DSLEEP_EN_OFFSET 7
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#define CRG_REG_LED_CLK_DSLEEP_EN_LEN 1
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#define CRG_REG_LED_CLK_DSLEEP_EN_OFFSET 6
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#define CRG_REG_SFCX2_CLK_DSLEEP_EN_LEN 1
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#define CRG_REG_SFCX2_CLK_DSLEEP_EN_OFFSET 5
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#define CRG_REG_SFC_CLK_DSLEEP_EN_LEN 1
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#define CRG_REG_SFC_CLK_DSLEEP_EN_OFFSET 4
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#define CRG_REG_PHY_CLK_DSLEEP_EN_LEN 1
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#define CRG_REG_PHY_CLK_DSLEEP_EN_OFFSET 3
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#define CRG_REG_ADC_IN_CLK_DSLEEP_EN_LEN 1
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#define CRG_REG_ADC_IN_CLK_DSLEEP_EN_OFFSET 2
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#define CRG_REG_DA_DATA_CLK_DSLEEP_EN_LEN 1
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#define CRG_REG_DA_DATA_CLK_DSLEEP_EN_OFFSET 1
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#define CRG_REG_TIME_CNT_CLK_DSLEEP_EN_LEN 1
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#define CRG_REG_TIME_CNT_CLK_DSLEEP_EN_OFFSET 0
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#define CRG_REG_TIME_CNT1_CLK_DSLEEP_EN_LEN 1
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#define CRG_REG_TIME_CNT1_CLK_DSLEEP_EN_OFFSET 6
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#define CRG_REG_NTB_CLK_DSLEEP_EN_LEN 1
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#define CRG_REG_NTB_CLK_DSLEEP_EN_OFFSET 5
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#define CRG_REG_PWM1_CLK_DSLEEP_EN_LEN 1
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#define CRG_REG_PWM1_CLK_DSLEEP_EN_OFFSET 4
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#define CRG_REG_MMU_CLK_DSLEEP_EN_LEN 1
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#define CRG_REG_MMU_CLK_DSLEEP_EN_OFFSET 3
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#define CRG_REG_TSENSOR_CLK_1M_DSLEEP_EN_LEN 1
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#define CRG_REG_TSENSOR_CLK_1M_DSLEEP_EN_OFFSET 2
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#define CRG_REG_SSP2_CLK_DSLEEP_EN_LEN 1
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#define CRG_REG_SSP2_CLK_DSLEEP_EN_OFFSET 1
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#define CRG_REG_OSC_APB_CLK_DSLEEP_EN_LEN 1
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#define CRG_REG_OSC_APB_CLK_DSLEEP_EN_OFFSET 0
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#define CRG_REG_TIME_CNT1_SRST_REQ_LEN 1
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#define CRG_REG_TIME_CNT1_SRST_REQ_OFFSET 0
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#define CRG_REG_PHY_D2LPF_SRST_REQ_LEN 1
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#define CRG_REG_PHY_D2LPF_SRST_REQ_OFFSET 0
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#define CRG_REG_XTAL_DS1_LEN 1
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#define CRG_REG_XTAL_DS1_OFFSET 2
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#define CRG_REG_XTAL_DS0_LEN 1
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#define CRG_REG_XTAL_DS0_OFFSET 1
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#define CRG_REG_XTAL_IO_EN_LEN 1
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#define CRG_REG_XTAL_IO_EN_OFFSET 0
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#endif // __CRG_REG_REG_OFFSET_FIELD_H__
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