143 lines
4.1 KiB
C
143 lines
4.1 KiB
C
/*
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* Copyright (c) CompanyNameMagicTag 2012-2019. All rights reserved.
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* Description: Upload SAR-ADC/PGA driver code. Pga_drv.c code
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* Author: CompanyName
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* Create: 2012-12-11
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*/
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#include "pga_drv.h"
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#include <soc_stdlib.h>
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#include <soc_mdm_task.h>
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pga_ctl g_pga_ctl = {
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0,
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};
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td_u32 uapi_pga_init(void)
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{
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reg_analog_wr44 pga_cfg_reg = {
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0,
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};
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reg_analog_wr40 pga_cfg_clk_gate = {
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0,
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};
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td_u32 ret = EXT_ERR_SUCCESS;
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uapi_task_pri_elevate();
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if (g_pga_ctl.is_init == TD_FALSE) {
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ret = uapi_sem_bcreate(&g_pga_ctl.pga_sem, "pga", EXT_SEM_ONE);
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if (ret == EXT_ERR_SUCCESS) {
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g_pga_ctl.is_init = TD_TRUE;
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} else {
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uapi_task_pri_resume();
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return ret;
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}
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}
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uapi_task_pri_resume();
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/* Configure initial value */
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pga_lock();
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REG_FORMAT_UAPI_U32(pga_cfg_reg) = com_bbp_reg_rd(REG_ANALOG_WR44);
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pga_cfg_reg.pd_pga0 = 0x1; /* powerdown */
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pga_cfg_reg.pd_pga1 = 0x1; /* powerdown */
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com_bbp_reg_wr(REG_ANALOG_WR44, &pga_cfg_reg);
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/* Other bits are configured to 0 */
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REG_FORMAT_UAPI_U32(pga_cfg_clk_gate) = com_bbp_reg_rd(REG_ANALOG_WR40);
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pga_cfg_clk_gate.clk_gate = 0x1;
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pga_cfg_clk_gate.buf_clk_sel = 0x0;
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pga_cfg_clk_gate.buf_clk_rst = 0x0;
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pga_cfg_clk_gate.buf_pd_clk = 0x0;
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pga_cfg_clk_gate.pga_clk_sel = 0x3;
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pga_cfg_clk_gate.pga_clk_rst = 0x0;
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pga_cfg_clk_gate.pga_pd_clk = 0x0;
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com_bbp_reg_wr(REG_ANALOG_WR40, &pga_cfg_clk_gate);
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pga_unlock();
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return ret;
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}
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td_u32 uapi_pga_amplify(EXT_CONST ext_pga_cfg *pga_cfg)
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{
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reg_analog_wr44 pga_cfg_reg = {
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0,
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};
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if (pga_cfg == TD_NULL) {
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return EXT_ERR_FAILURE;
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}
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if ((td_u32)pga_cfg->pga_idx & EN_PGA_0) {
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if ((pga_cfg->pga0_gain == EN_PGA_GAIN_NA) || (pga_cfg->pga0_lp == EN_PGA_LP_NA)) {
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return EXT_ERR_FAILURE;
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}
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}
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if ((td_u32)pga_cfg->pga_idx & EN_PGA_1) {
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if ((pga_cfg->pga1_gain == EN_PGA_GAIN_NA) || (pga_cfg->pga1_lp == EN_PGA_LP_NA)) {
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return EXT_ERR_FAILURE;
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}
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}
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uapi_task_pri_elevate();
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if (g_pga_ctl.is_init == TD_FALSE) {
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uapi_task_pri_resume();
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return EXT_ERR_FAILURE;
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}
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uapi_task_pri_resume();
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pga_lock();
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REG_FORMAT_UAPI_U32(pga_cfg_reg) = com_bbp_reg_rd(REG_ANALOG_WR44);
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if ((td_u32)pga_cfg->pga_idx & EN_PGA_0) {
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pga_cfg_reg.pga0_gain = pga_cfg->pga0_gain;
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pga_cfg_reg.pga0_lp = pga_cfg->pga0_lp;
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pga_cfg_reg.pga_vcm_sel = pga_cfg->pga_vcm_sel;
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pga_cfg_reg.pd_pga0 = 0x0; /* Operating mode */
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}
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if ((td_u32)pga_cfg->pga_idx & EN_PGA_1) {
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pga_cfg_reg.pga1_gain = pga_cfg->pga1_gain;
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pga_cfg_reg.pga1_lp = pga_cfg->pga1_lp;
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pga_cfg_reg.pga_vcm_sel = pga_cfg->pga_vcm_sel;
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pga_cfg_reg.pd_pga1 = 0x0; /* Operating mode */
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}
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com_bbp_reg_wr(REG_ANALOG_WR44, &pga_cfg_reg);
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pga_unlock();
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return EXT_ERR_SUCCESS;
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}
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td_u32 uapi_pga_deinit(void)
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{
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reg_analog_wr44 pga_cfg_reg = {
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0,
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};
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td_u32 ret = EXT_ERR_SUCCESS;
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uapi_task_pri_elevate();
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if (g_pga_ctl.is_init == TD_FALSE) {
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uapi_task_pri_resume();
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return EXT_ERR_FAILURE;
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}
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uapi_task_pri_resume();
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pga_lock();
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/* Restore initial value */
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REG_FORMAT_UAPI_U32(pga_cfg_reg) = com_bbp_reg_rd(REG_ANALOG_WR44);
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pga_cfg_reg.pd_pga0 = 0x1; /* powerdown */
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pga_cfg_reg.pd_pga1 = 0x1; /* powerdown */
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pga_cfg_reg.pga_vcm_sel = EN_PGA_VCM_SEL_0_4V;
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pga_cfg_reg.pga0_lp = EN_PGA_LP_NA;
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pga_cfg_reg.pga1_lp = EN_PGA_LP_NA;
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pga_cfg_reg.pga0_gain = EN_PGA_GAIN_25;
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pga_cfg_reg.pga1_gain = EN_PGA_GAIN_25;
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com_bbp_reg_wr(REG_ANALOG_WR44, &pga_cfg_reg);
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pga_unlock();
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if (g_pga_ctl.is_init == TD_TRUE) {
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ret = uapi_sem_delete(g_pga_ctl.pga_sem);
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if (ret == EXT_ERR_SUCCESS) {
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(td_void)memset_s((void *)&g_pga_ctl, sizeof(g_pga_ctl), 0x0, sizeof(g_pga_ctl));
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}
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}
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return ret;
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}
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