126 lines
3.6 KiB
ArmAsm
126 lines
3.6 KiB
ArmAsm
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.syntax unified
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.arch armv7-m
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.cpu cortex-m3
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.thumb
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.global Reset_Handler
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.extern __bss_begin__
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.extern __bss_end__
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.extern __bss_size__
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.extern __data_begin__
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.extern __SYSTEM_STACK_BEGIN__
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.extern __SYSTEM_STACK_END__
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#ifdef LIB_CONFIGURABLE
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.extern __rom_bss_begin__
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.extern __rom_bss_end__
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.extern __rom_bss_size__
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#endif
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.extern main
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.equ SHCSR, 0xE000ED24
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.equ BUSFAULTSET, 0x00020000
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.equ SCBCCR, 0xE000ED14
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.equ DIV0TRPMSK, 0x00000010
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/******************************************************************************
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*
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* The stack for MSP of Cortex M3.
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*
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*******************************************************************************/
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.section .stacks,"aw",%progbits
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.set STACK_SIZE_SYSTEM, 0x00000900 /* Set the stack size for MSP */
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.global stack_system
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.type stack_system, %object
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.align 3
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stack_system_end:
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.space STACK_SIZE_SYSTEM
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.size stack_system_end, . - stack_system_end
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stack_system:
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.size stack_system, . - stack_system
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/******************************************************************************
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*
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* The entry Reset_Handler
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*
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*******************************************************************************/
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.section .text.Reset_Handler,"ax",%progbits
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.weak Reset_Handler
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.type Reset_Handler, %function
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.func Reset_Handler
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.align 2
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.thumb
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Reset_Handler:
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cpsid i
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/* Make sure SP is really at the start of the stack */
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ldr r0, =stack_system
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msr msp, r0
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/* Prefill the system stack with 0xefbeadde (or deafbeef in little endian) */
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ldr r1, =__SYSTEM_STACK_BEGIN__
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ldr r3, =__SYSTEM_STACK_END__
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stack_fill:
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subs r3, r3, r1
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beq stack_fill_loop_end
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ldr r2, =0xefbeadde
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stack_fill_loop:
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str r2, [r1, #0] /* Store the quad octet initialisation value in r2 into address in r1 */
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adds r1, r1, #4 /* Increased address in r1 by a quad octet */
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subs r3, r3, #4 /* Decrease the number of bytes to do by a quad octet */
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bgt stack_fill_loop /* Keep going until it is all done */
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stack_fill_loop_end:
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/* Clear bss section */
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ldr r1, =__bss_begin__
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ldr r3, =__bss_end__
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subs r3, r3, r1
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beq end_clear_bss_loop
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ldr r2, =#00000000
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clear_bss_loop:
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str r2, [r1, #0] /* Store the octet initialisation value in r2 into address in r1 */
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adds r1, r1, #4 /* Increased address in r1 by an octet */
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subs r3, r3, #4 /* Decrease the number of bytes to do by an octet */
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bgt clear_bss_loop /* Keep going until it is all done */
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end_clear_bss_loop:
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#ifdef LIB_CONFIGURABLE
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/* Clear rom bss section */
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ldr r1, =__rom_bss_begin__
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ldr r3, =__rom_bss_end__
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subs r3, r3, r1
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beq end_clear_rom_bss_loop
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ldr r2, =#00000000
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clear_rom_bss_loop:
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str r2, [r1, #0] /* Store the octet initialisation value in r2 into address in r1 */
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adds r1, r1, #4 /* Increased address in r1 by an octet */
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subs r3, r3, #4 /* Decrease the number of bytes to do by an octet */
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bgt clear_rom_bss_loop /* Keep going until it is all done */
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end_clear_rom_bss_loop:
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#endif
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#ifdef USE_REMAP
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/*enable busfault int*/
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ldr r4, =SHCSR
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ldr r5, =BUSFAULTSET
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str r5, [r4]
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#endif
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/*enable div 0 trigger*/
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ldr r4, =SCBCCR
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ldr r5, =DIV0TRPMSK
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ldr r3, [r4]
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orr r3, r3, r5
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str r3, [r4]
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cpsie i
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ldr pc, =main
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.size Reset_Handler, .-Reset_Handler
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.endfunc
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