80 lines
2.0 KiB
C
80 lines
2.0 KiB
C
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/*
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* Copyright (c) CompanyNameMagicTag 2012-2019. All rights reserved.
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* Description: Upload SAR-ADC/PGA driver code. Pga_drv.h code
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* Author: CompanyName
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* Create: 2012-12-11
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*/
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#ifndef __PGA_DRV_H__
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#define __PGA_DRV_H__
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#include <soc_mdm_pga.h>
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#include <soc_mdm_sem.h>
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#include <soc_mdm_types.h>
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#include <soc_mdm_isr.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct {
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td_bool is_init;
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td_u8 resv[3]; /* keep 3 bytes for alignment */
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td_u32 pga_sem;
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} pga_ctl;
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extern pga_ctl g_pga_ctl;
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#define pga_lock() \
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do { \
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if (uapi_is_int_context() == 0) { \
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uapi_sem_wait(g_pga_ctl.pga_sem, EXT_SYS_WAIT_FOREVER); \
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} \
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} while (0)
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#define pga_unlock() \
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do { \
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if (uapi_is_int_context() == 0) { \
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uapi_sem_signal(g_pga_ctl.pga_sem); \
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} \
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} while (0)
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#define REG_PGA_BASE 0x40040000
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#define REG_ANALOG_WR40 (REG_PGA_BASE + 0x34)
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#define REG_ANALOG_WR44 (REG_PGA_BASE + 0x38)
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/* REG_ANALOG_WR40 */
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typedef struct {
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td_u32 resv1 : 7;
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td_u32 clk_gate : 1;
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td_u32 buf_clk_sel : 2;
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td_u32 buf_clk_rst : 1;
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td_u32 buf_pd_clk : 1;
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td_u32 pga_clk_sel : 2;
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td_u32 pga_clk_rst : 1;
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td_u32 pga_pd_clk : 1;
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td_u32 rsvd2 : 16;
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} reg_analog_wr40;
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/* REG_ANALOG_WR44 */
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typedef struct {
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td_u32 sar_vcm_debug : 2;
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td_u32 pd_pga0 : 1;
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td_u32 pd_pga1 : 1;
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td_u32 pga_ctune : 4;
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td_u32 pga0_gain : 1;
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td_u32 pga1_gain : 1;
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td_u32 pga_vcm_sel : 2;
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td_u32 pga0_lp : 2;
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td_u32 pga1_lp : 2;
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td_u32 resv1 : 16;
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} reg_analog_wr44;
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#ifdef __cplusplus
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}
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#endif
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#endif
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