67 lines
3.7 KiB
C
67 lines
3.7 KiB
C
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/*
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* Copyright (c) CompanyNameMagicTag 2018-2019. All rights reserved.
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* File name : crg_reg_reg_offset.h
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* Project line : Platform And Key Technologies Development
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* Department : CAD Development Department
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* Version : 1.0
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* Date : 2013/3/10
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* Description : The description of xxx project
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* Others : Generated automatically by nManager V4.2
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* History : xxx 2018/05/19 17:32:50 Create file
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*/
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#ifndef __CRG_REG_OFFSET_H__
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#define __CRG_REG_OFFSET_H__
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/* CRG_REG Base address of Module's Register */
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#define DW21_CRG_REG_BASE EXT_CRG_REG_BASE
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/***************************************************************************** */
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/* xxx CRG_REG Registers' Definitions */
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/***************************************************************************** */
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#define DW21_CRG_REG_SC_PLLLOCK_STAT_REG (DW21_CRG_REG_BASE + 0x0)
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/* SC_PLLLOCK_STAT is the PLL lock status indicator register. */
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#define DW21_CRG_REG_SC_APLL_CTRL0_REG (DW21_CRG_REG_BASE + 0x4)
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/* SC_APLL_CTRL0 is ARM PLL control register 0. */
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#define DW21_CRG_REG_SC_APLL_CTRL1_REG (DW21_CRG_REG_BASE + 0x8)
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/* SC_APLL_CTRL1 is ARM PLL control register 1. */
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#define DW21_CRG_REG_SC_PERI_CLKEN0_REG (DW21_CRG_REG_BASE + 0x14)
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/* SC_PERI_CLKEN is peripheral clock enable register 0. */
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#define DW21_CRG_REG_SC_PERI_CLKEN1_REG (DW21_CRG_REG_BASE + 0x18)
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/* SC_PERI_CLKEN is peripheral clock enable register 1. */
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#define DW21_CRG_REG_SC_PERI_CLKSTAT0_REG (DW21_CRG_REG_BASE + 0x1C)
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/* SC_PERI_CLKSTAT is peripheral clock status indicator register 0. */
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#define DW21_CRG_REG_SC_PERI_CLKSTAT1_REG (DW21_CRG_REG_BASE + 0x20)
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/* SC_PERI_CLKSTAT is peripheral clock status indicator register 1. */
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#define DW21_CRG_REG_SC_PERI_CLKSEL_REG (DW21_CRG_REG_BASE + 0x24)
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/* SC_PERI_CLKSEL is the peripheral clock source select register. */
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#define DW21_CRG_REG_SC_PERI_SRST_REG (DW21_CRG_REG_BASE + 0x28)
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/* SC_PERI_SRST is the peripheral soft reset request register. */
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#define DW21_CRG_REG_SC_SLEEP0_CTRL_REG (DW21_CRG_REG_BASE + 0x2C)
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/* SC_SLEEP0_CTRL is the low-power clock sleep enable register for each module. */
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#define DW21_CRG_REG_SC_PHY_CLK_EN_REG (DW21_CRG_REG_BASE + 0x30)
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/* SC_PHY_CLK_EN is the PHY clock gating software control register. */
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#define DW21_CRG_REG_SC_PHY_SRST_REG (DW21_CRG_REG_BASE + 0x34)
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/* SC_PHY_SRST is the PHY soft reset control register. */
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#define DW21_CRG_REG_SC_PHY_RST_MASK_REG (DW21_CRG_REG_BASE + 0x38)
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/* SC_PHY_RST_MASK is the PHY reset mask register. */
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#define DW21_CRG_REG_MEM_TOP_GATE_EN_REG (DW21_CRG_REG_BASE + 0x3C)
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/* MEM_TOP clock gating register */
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#define DW21_CRG_REG_BOOT_ROM_GATE_EN_REG (DW21_CRG_REG_BASE + 0x40)
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/* Bootrom clock gating register */
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#define DW21_CRG_REG_SC_PHY_RST1_MASK_REG (DW21_CRG_REG_BASE + 0x44)
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/* SC_PHY_RST_MASK is PHY reset mask register 1. */
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#define DW21_CRG_REG_SC_SLEEP1_CTRL_REG (DW21_CRG_REG_BASE + 0x48)
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/* SC_SLEEP1_CTRL is the low-power clock sleep enable register for each module. */
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#define DW21_CRG_REG_SC_DEEP_SLEEP0_CTRL_REG (DW21_CRG_REG_BASE + 0x4C)
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/* SC_DEEP_SLEEP0_CTRL is the low-power clock sleep enable control register for each module. */
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#define DW21_CRG_REG_SC_DEEP_SLEEP1_CTRL_REG (DW21_CRG_REG_BASE + 0x50)
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/* SC_DEEP_SLEEP1_CTRL is the low-power clock sleep enable register for each module. */
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#define DW21_CRG_REG_SC_PERI_SRST1_REG (DW21_CRG_REG_BASE + 0x54)
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/* SC_PERI_SRST1 is the peripheral soft reset request register. */
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#define DW21_CRG_REG_SC_PHY1_SRST1_REG (DW21_CRG_REG_BASE + 0x58)
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/* SC_PHY_SRST1 is the PHY soft reset control register. */
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#define DW21_CRG_REG_XTAL_IO_CTRL_REG (DW21_CRG_REG_BASE + 0x5C)
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/* Crystal I/O configuration register */
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#endif // __CRG_REG_REG_OFFSET_H__
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